Core Packages

Wishbone boot ROM component and a collection of basic boot loaders for OpenRISC…

The award-winning SERV, the world's smallest RISC-V CPU

Simple reference system for SERV

Convenience wrapper for SERV

Verilog CDC implementations

Generic FIFO

SPI device for loading data to RAM

FIFOs and size converters for data streams

Wishbone BFM

Common Wishbone definitions

Wishbone Bus Interconnect utilities

Wishbone RAM with selectable backends

Wishbone read/write AXI streamer core

BaseJump STL: A Standard Template Library for SystemVerilog (Hardened)

BaseJump STL: A Standard Template Library for SystemVerilog (Nonsynthesizable)

BaseJump STL: A Standard Template Library for SystemVerilog

Verilog arbiter

Berkeley Verilog HardFloat (mirror by University of Washington)

Example LED blinking project for your FPGA dev board of choice

A collection of core generators to use with FuseSoC

Verilog test bench utilities

stable release (downloaded from GitHub); AXI related modules see https://github…

stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...…

stable release (downloaded from GitHub); see https://github.com/enclustra/en_c…

stable release (downloaded from GitHub); Fixed point mathematics see https://gi…

stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SP…

stable release (downloaded from GitHub); olo_fix tutorial for open-logic, targe…

stable release (downloaded from GitHub); quartus tutorial for open-logic, targe…

stable release (downloaded from GitHub); vivado tutorial for open-logic, target…

Common SystemVerilog components