FuseSoC Package Directory
award-winning
Libraries
award-winning:openrisc
Cores
Download
award-winning:openrisc:or1k_bootloaders:0.9.1
signed
Wishbone boot ROM component and a collection of basic boot loaders for OpenRISC…
.core
.sig
award-winning:serv
Cores
Download
award-winning:serv:serv:1.3.0
signed
The award-winning SERV, the world's smallest RISC-V CPU
.core
.sig
award-winning:serv:serv:1.4.0
unsigned
The award-winning SERV, the world's smallest RISC-V CPU
.core
award-winning:serv:servant:1.3.0
signed
Simple reference system for SERV
.core
.sig
award-winning:serv:servant:1.4.0
unsigned
Simple reference system for SERV
.core
award-winning:serv:servile:1.3.0
signed
Convenience wrapper for SERV
.core
.sig
award-winning:serv:servile:1.4.0
unsigned
Convenience wrapper for SERV
.core
award-winning:serv:serving:1.4.0
unsigned
SERV-based subsystem for FPGAs
.core
award-winning:soc
Cores
Download
award-winning:soc:underserved:0.1.0
unsigned
SERV-based RISC-V SoC for Tiny Tapeout
.core
award-winning:utils
Cores
Download
award-winning:utils:cdc_utils:0.1.0
signed
Verilog CDC implementations
.core
.sig
award-winning:utils:fifo:1.3.0
signed
Generic FIFO
.core
.sig
award-winning:utils:spi_ram_loader:0.0.1
unsigned
SPI device for loading data to RAM
.core
award-winning:utils:stream_utils:1.3.0
signed
FIFOs and size converters for data streams
.core
.sig
award-winning:wishbone
Cores
Download
award-winning:wishbone:wb_bfm:1.2.1
signed
Wishbone BFM
.core
.sig
award-winning:wishbone:wb_common:1.0.3
signed
Common Wishbone definitions
.core
.sig
award-winning:wishbone:wb_intercon:1.4.1
signed
Wishbone Bus Interconnect utilities
.core
.sig
award-winning:wishbone:wb_ram:1.1.0
unsigned
Wishbone RAM with selectable backends
.core
award-winning:wishbone:wb_streamer:1.1.0
signed
Wishbone read/write AXI streamer core
.core
.sig